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8k x 9 fifo, 16k x 9 fifo 32k x 9 fifo with programmable flags CY7C470 cy7c472 cy7c474 cypress semiconductor corporation ? 3901 north first street ? san jose ? ca 95134 ? 408-943-2600 december 1990 C revised april 1995 1cy 7 c47 4 features ? 8k x 9, 16k x 9, and 32k x 9 fifo buffer memory ? asynchronous read/write ? high-speed 33.3-mhz read/write independent of depth/width ? low operating power i cc (max.) = 70 ma ? programmable almost full/empty flag ? empty, almost empty, half full, almost full, and full status flags ? programmable retransmit ? expandable in width ? 5v 10% supply ? ttl compatible ? three-state outputs ? proprietary 0.8-micron cmos technology functional description the cyc47x fifo series consists of high-speed, low-power, first-in first-out (fifo) memories with programmable flags and retransmit mark. the CY7C470, cy7c472, and cy7c474 are 8k, 16k, and 32k words by 9 bits wide, respectively. they are offered in 600-mil dip, plcc, and lcc pa ckag es. each fifo memory is organized such that the data is read in the same sequ ential order that it was written. three status pinsemp- ty/full (e /f ), programmable almost full/empty (pafe ), and half full (hf )are provided to the user. these pins are de- coded to deter mine one of six states: empty, almost empty, less than half full, greater than half full, almost full, and full. the read and wr ite operations may be asy nchronous; each can occur at a rate of 33.3 mhz. the write operation occurs when the wr ite (w ) signal goes low. read occurs when read (r ) goes low. the nine data outputs go into a high-imped- ance state when r is high. the user can store the value of the read pointer for retransmit by using the mark pin. a low on the retransmit (rt ) input causes the fifo to resend data by resetting the read pointer to the value stored in the mark pointer. in the standalone and width expansion configurations, a low on the retransmit (rt ) input causes the fifo to resend the data. with the mark feature, retransmit can start from any word in the fifo. the cyc47x series is fabricated using a proprietary 0.8-mi- cron n-well cmos tech nology. input esd protection is greater than 2001v and latch-up is prevented by the use of reliable layout techniques, guard rings, and a substrate bias generator. logic block diagram pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 15 16 17 18 19 20 24 23 22 21 13 14 25 28 27 26 top view dip w d 8 d 3 d 2 d 1 d 0 mark pafe q 0 q 1 q 2 gnd v cc d 4 rt mr e /f hf q 7 r plcc/lcc top view q 3 q 8 d 5 d 6 d 7 q 6 q 5 q 4 4 3 2 1 32 31 30 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 rt mr e /f hf q 7 d 6 q 6 d 7 nc mark pointer write pointer reset logic ram array 8k x 9 16k x 9 32k x 9 datainputs (d 0 Cd 8 ) threeC state buffers dataoutputs (q 0 Cq 8 ) read pointer flag logic e /f pafe mr rt d 2 d 1 d 0 mark pafe q 0 q 1 nc q 2 7c470C1 7c470C2 7c470C3 7c470 7c472 7c474 7c470 7c472 7c474 w hf mark r programmable flag register
CY7C470 cy7c472 cy7c474 2 maximum ratings storage temperature ................................. C65 c to +150 c ambient temperature with power applied............................................. C55 c to +125 c supply voltage to ground potential ............... C0.5v to +7.0v dc voltage applied to outputs in high z state ............................................... C0.5v to +7.0v dc input voltage............................................ C3.0v to +7.0v power dissipation ..........................................................1.0w output current, into outputs (low) ............................ 20 ma static discharge voltage ........................................... >2001v (per mil-std-883, method 3015) latch-up current ..................................................... >200 ma selection guide 7c470C15 7c472C15 7c474C15 7c470C20 7c472C20 7c474C20 7c470C25 7c472C25 7c474C25 7c470C40 7c472C40 7c474C40 frequency (mhz) 33.3 33.3 28.5 20 maximum access time (ns) 15 20 25 40 maximum operating current (ma) commercial 105 military/industrial operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% industrial C40 c to +85 c 5v 10% military [1] C55 c to +125 c 5v 10% electrical characteristics over the operating range [2] 7c470C15 7c472C15 7c474C15 7c470C20 7c472C20 7c474C20 7c470C25 7c472C25 7c474C25 parame- ter description test conditions min. max. min. max. min. max. unit v oh output high voltage v cc = min., i oh = C2.0 ma 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 v v ih coml 2.2 2.2 v mil/ind 2.2 2.2 v il input low voltage 0.8 0.8 0.8 v i ix input leakage current gnd v i v cc C10 +10 C10 +10 C10 +10 m a i oz output leakage current r 3 v ih , gnd v o v cc C10 +10 C10 +10 C10 +10 m a i cc operating current v cc = max., i out = 0 ma coml 105 90 ma mil/ind 110 95 i sb1 standby current all inputs = v ih min. coml 25 25 ma mil/ind 30 30 i sb2 power-down current all inputs = v cc C0.2v coml 20 20 ma mil/ind 25 25 i os [3] output short circuit current v cc = max., v out = gnd C90 C90 C90 ma notes: 1. t a is the instant on case temperature. 2. see the last page of this specification for group a subgroup testing information. 3. not more than one output should be tested at a time. duration of the short circuit should not be more than one second.
CY7C470 cy7c472 cy7c474 3 electrical characteristics over the operating range [2] (continued) 7c470C40 7c472C40 7c474C40 parameter description test conditions min. max. unit v oh output high voltage v cc = min., i oh = C2.0 ma 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 v v ih input high voltage coml 2.2 v mil/ind 2.2 v il input low voltage 0.8 v i ix input leakage current gnd v i v cc C10 +10 m a i oz output leakage current r 3 v ih , gnd v o v cc C10 +10 m a i cc operating current v cc = max., i out = 0 ma coml 70 ma mil/ind 75 i sb1 standby current all inputs = v ih min. coml 25 ma mil/ind 30 i sb2 power-down current all inputs = v cc C0.2v coml 20 ma mil/ind 25 i os [3] output short circuit current v cc = max., v out = gnd C90 ma capacitance [4] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 4.5v 10 pf c out output capacitance 12 pf ac test loads and waveforms note: 4. tested initially and after any design or process changes that may affect these parameters. 3.0v 5v output r1 500 w r2 333 w 30 pf including jigand scope gnd 90% 10% 90% 10% 5ns 5 ns 5v output r1 500 w r2 333 w 5pf including jig and scope output 2v equivalent to: thvenin equivalent (b) (a) 7c470C4 7c470C5 7c470C6 all input pulses 200 w
CY7C470 cy7c472 cy7c474 4 switching characteristics over the operating range [5, 6] 7c470C15 7c472C15 7c474C15 7c470C20 7c472C20 7c474C20 7c470C25 7c472C25 7c474C25 7c470C40 7c472C40 7c474C40 parameter description min. max. min. max. min. max. min. max. unit t cy cycle time 30 30 35 50 ns t a access time 15 20 25 40 ns t rv recovery time 15 10 10 10 ns t pw pulse width 15 20 25 40 ns t lzr read low to low z 3 3 3 3 ns t dv [7] valid data from read high 3 3 3 3 ns t hz [7] read high to high z 15 15 18 25 ns t hwz write high to low z 5 5 5 5 ns t sd data set-up time 11 12 15 20 ns t hd data hold time 0 0 0 0 ns t efd e /f delay 15 20 25 40 ns t efl mr to e /f low 25 30 35 50 ns t hfd hf delay 25 30 35 50 ns t afed pafe delay 25 30 35 50 ns t rae effective read from write high 15 20 25 40 ns t waf effective write from read high 15 20 25 40 ns notes: 5. test conditions assume signal transmission time of 5 ns or less, timing reference levels of 1.5v and output loading of the specified i ol /i oh and 30-pf load capacitance, as in part (a) of ac test load and waveforms, unless otherwise specified. 6. see the last page of this specification for group a subgroup testing information. 7. t hzr and t dvr use capacitance loading as in part (b) of ac test loads. t hzr transition is measured at +500 mv from v ol and C500 mv from v oh . t dvr transition is measured at the 1.5v level. t hwz and t lzr transition is measured at 100 mv from the steady state.
CY7C470 cy7c472 cy7c474 5 switching waveforms notes: 8. waveform labels in parentheses pertain to writing the programmable flag reg ister from the output port (q 0 C q 8 ). 9. master reset (mr ) must be pulsed low once prior to programming. t rv asynchronous read and write 7c470C7 data valid data valid data valid data valid t sd t hd t cy t pw t a t rv t a t lzr t dvr t hzr t cy t pw t rv r q 0 Cq 8 w d 0 Cd 8 masterreset (no write to programmable flag register) mr r ,w e /f pafe hf t cy t pw t hfd t efl t afed t rv t rv mr w (r ) 7c470C8 7c470C9 t rv t pw t rv t rv valid d 0 Cd 8 (q 0 Cq 8 ) t hd t pw t sd t hd t cy t cy t pw t cy master reset (write to programmable flag register) [8,9]
CY7C470 cy7c472 cy7c474 6 switching waveforms (continued) w r e/f flag (last write to first read full flag) half full flag 7c470C10 7c470C11 7c470C12 fullC1 full fullC1 t efd w e /f t efd hf r e /f t efd hf e /f flag (last read to first write empty flag) empty+1 empty empty+1 halfCfull r t hfd w hf t hfd halfCfull +1 halfCfull high low t efd
CY7C470 cy7c472 cy7c474 7 note: 10. the flags may change state during retransmit, but they will be valid a t cy later, except for the cy7c47xC20 (m ilitary), whose flags will be valid after t cy + 10 ns. switching waveforms (continued) w r pafe flag (almost full) t afed w pafe t afed hf r pafe flag (almost empty) t afed pafe t afed hf w ,r t cy t cy t rv t pw t rv rt t a data valid t lzr q 0 Cq 8 7c470C13 7c470C14 7c470C15 t cy high low flags v alid retransmit [10] flags [10]
CY7C470 cy7c472 cy7c474 8 switching waveforms (continued) w ,r mark t cy t cy t rv t pw t rv mark r empty flag and read data flow-through mode e /f data valid data out w data in t rae t pw t efd t efd t a t hwz 7c470C16 7c470C17
CY7C470 cy7c472 cy7c474 9 architecture the CY7C470, cy7c472, and cy7c474 fifos consist of an array of 8,192, 16,384, and 32,768 words of 9 bits each, re- spectively. the control consists of a read pointer, a write point- er, a retransmit pointer, control signals (i. e., write, read, mark, retransmit, and master reset), and flags (i.e., empty/full, half full, and programmable almost full/empty). resetting the fifo upon power-up, the fifo must be reset with a master reset (mr ) cycle. this causes the fifo to enter the empty condition signi- fied by the empty flag (e /f ) and almost full/empty flag (pafe ) being low, and half full flag (hf ) being high. the read pointer, write pointer, and retransmit pointer are reset to zero. for a valid reset, read (r ) and write (w ) must be high t rpw /t wpw before the falling edge and t rmr after the rising edge of mr . writing data to the fifo data can be written to the fifo when it is not full [11] . a falling edge of w initiates a write cycle. data appearing at the inputs (d 0 Cd 8 ) t sd before and t hd after the rising edge of w will be stored sequen- tially in the fifo. reading data from the fifo data can be read from the fifo when it is not empty [12] . a falling edge of r initiates a read cycle. data outputs (q 0 Cq 8 ) are in a high-impedance condition when the fifo is empty and between read operations (r high). the falling edge of r during the last read cycle before the empty condition triggers a high-to-low transition of e /f , pro- hibiting any further read operations until t rff after a valid write. retransmit the retransmit feature is beneficial when transferring packets of data. it enables the receipt of data to be acknowledged by the receiver and resent if necessary. retransmission can start from anywhere in the fifo and be repeated without limitation. the retransmit methodology is as follows: mark the current value of the read pointer, after an er ror in subsequent read operations return to that location and resume reading. this effectively resends all of the data from the mark point. when mark is low, the current value of the read pointer is stored. this operation marks the beginning of the packet to be resent. when rt is low, the read pointer is updated with the mark location. during each subsequent read cycle, data is read and the read pointer incre- mented. care must be taken when using the retransmit feature. use the mark function such that the write pointer does not pass the mark pointer, because fur ther write operations will overwrite data. programmable almost full/empty flag the CY7C470/2/4 o ffer a variable offset for the almost empty and the almost full condition. the offset is loaded into the programmable flag register (pfr) during a master reset cycle. while mr is low, the pfr can be loaded from q 8 Cq 0 by pulsing r low or from d 8 Cd 0 by pulsing w low. the offset options are listed in table 2 . see table 1 for a description of the six fifo states. if the pfr is not loaded during master reset (r and w high) the default offset will be 256 words from full and empty. switching waveforms (continued) r full flag and write data flow-through mode e /f data out w t a t sd data in t hd t waf t pw t efd t efd 7c470C18 data valid data valid notes: 11. when the fifo is less than half full, the flags make a low-to-high transi tion on the rising edge of w and make the high-to-low transition on the falling edge of r . if the fifo is more than half full, the flags make the low-to-high transition on the rising edge of r and high-to-low transition on the fa lling edge of w . 12. full and em pty states can be decoded from the half-full (hf ) and empty/full (e /f ) flags.
CY7C470 cy7c472 cy7c474 10 table 1. flag truth table [13] hf e /f pafe state cy77c470 (8k x 9) number of words in fifo cy77c472 (16k x 9) number of words in fifo cy77c474 (32k x 9) number of words in fifo 1 0 0 empty 0 0 0 1 1 0 almost empty 1 t (p C 1) 1 t (p C 1) 1 t (p C 1) 1 1 1 less than half full p t 4096 p t 8192 p t 16384 0 1 1 greater than half full 4097 t (8192 C p) 8193 t (16384 C p) 16385 t (32768 C p) 0 1 0 almost full (8192 C p+1) t 8191 (16384 C p+1) t 16383 (32768 C p+1) t 32767 0 0 0 full 8192 16384 32768 table 2. programmable almost full/empty options [14] d3 d2 d1 d0 pafe active when: p 0 0 0 0 256 or less locations from empty/full (default) 256 0 0 0 1 16 or less locations from empty/full 16 0 0 1 0 32 or less locations from empty/full 32 0 0 1 1 64 or less locations from empty/full 64 0 1 0 0 128 or less locations from empty/full 128 0 1 0 1 256 or less locations from empty/full (default) 256 0 1 1 0 512 or less locations from empty/full 512 0 1 1 1 1024 or less locations from empty/full 1024 1 0 0 0 2048 or less locations from empty/full 2048 1 0 0 1 4098 or less locations from empty/full [15] 4098 1 0 1 0 8192 or less locations from empty/full [16] 8192 notes: 13. see table 2 for p values. 14. almost flags default to 256 locations from empty/full. 15. only for cy7c472 and cy7c474. 16. only for CY7C470.
CY7C470 cy7c472 cy7c474 11 typical ac and dc characteristics 0.60 0.80 1.00 1.20 1.40 1.60 C55.00 5.00 65.00 125.00 0.80 0.90 1.00 1.10 1.20 4.00 4.50 5.00 5.50 6.00 supply voltage (v) normalized t a vs.supply voltage normalized supply current vs. supply voltage normalized t a vs. ambient temperature ambient temperature ( c) capacitance (pf) typical t a change vs. output loading normalized supply current vs. ambient temperature t a =25 c frequency (mhz) normalized supply current vs.frequency supply voltage (v) output voltage (v) output source current vs. output voltage 0.00 5.00 10.00 15.00 20.00 0.00 500.00 1000.00 v cc =5.0v v cc =5.0v t a =25 c 0.60 0.80 1.00 1.20 1.40 4.00 4.50 5.00 5.50 6.00 output sink current vs. output voltage output voltage (v) ambient temperature ( c) v in =3.0v t a =25 c f= 33 mhz 0.80 0.90 1.00 1.10 1.20 C55.00 5.00 65.00 125.00 v in =3.0v t a =25 c f= 33mhz 0.60 0.70 0.80 0.90 1.00 1.10 15.00 20.00 25.00 30.00 35.00 v cc =5.0v t a =25 c v in =3.0v 0.00 10.00 20.00 30.00 40.00 50.00 0.00 1.00 2.00 3.00 4.00 v cc =5.0v t a =25 c 0.00 20.00 40.00 60.00 80.00 100.00 0.00 1.00 2.00 3.00 4.00 v cc =5.0v t a =25 c
CY7C470 cy7c472 cy7c474 12 ordering information speed (ns) ordering code package name package type operating range 15 CY7C470C15jc j65 32-lead plastic leaded chip carrier commercial CY7C470C15pc p15 28-lead (600-mil) molded dip CY7C470C15ji j65 32-lead plastic leaded chip carrier industrial 20 CY7C470C20dmb d43 28-lead (600-mil) sidebraze cerdip military CY7C470C20lmb l55 32-pin rectangular leadless chip carrier 25 CY7C470C25jc j65 32-lead plastic leaded chip carrier commercial CY7C470C25pc p15 28-lead (600-mil) molded dip CY7C470C25ji j65 32-lead plastic leaded chip carrier industrial CY7C470C25dmb d43 28-lead (600-mil) sidebraze cerdip military CY7C470C25lmb l55 32-pin rectangular leadless chip carrier 40 CY7C470C40jc j65 32-lead plastic leaded chip carrier commercial CY7C470C40pc p15 28-lead (600-mil) molded dip CY7C470C40ji j65 32-lead plastic leaded chip carrier industrial CY7C470C40dmb d43 28-lead (600-mil) sidebraze cerdip military CY7C470C40lmb l55 32-pin rectangular leadless chip carrier speed (ns) ordering code package name package type operating range 15 cy7c472C15jc j65 32-lead plastic leaded chip carrier commercial cy7c472C15pc p15 28-lead (600-mil) molded dip cy7c472C15ji j65 32-lead plastic leaded chip carrier industrial 20 cy7c472C20dmb d43 28-lead (600-mil) sidebraze cerdip military cy7c472C20lmb l55 32-pin rectangular leadless chip carrier 25 cy7c472C25jc j65 32-lead plastic leaded chip carrier commercial cy7c472C25pc p15 28-lead (600-mil) molded dip cy7c472C25ji j65 32-lead plastic leaded chip carrier industrial cy7c472C25dmb d43 28-lead (600-mil) sidebraze cerdip military cy7c472C25lmb l55 32-pin rectangular leadless chip carrier 40 cy7c472C40jc j65 32-lead plastic leaded chip carrier commercial cy7c472C40pc p15 28-lead (600-mil) molded dip cy7c472C40ji j65 32-lead plastic leaded chip carrier industrial cy7c472C40dmb d43 28-lead (600-mil) sidebraze cerdip military cy7c472C40lmb l55 32-pin rectangular leadless chip carrier
CY7C470 cy7c472 cy7c474 13 military specifications group a subgroup testing document #: 38C00142Ch ordering information (continued) speed (ns) ordering code package name package type operating range 15 cy7c474C15jc j65 32-lead plastic leaded chip carrier commercial cy7c474C15pc p15 28-lead (600-mil) molded dip cy7c474C15ji j65 32-lead plastic leaded chip carrier industrial 20 cy7c474C20dmb d43 28-lead (600-mil) sidebraze cerdip military cy7c474C20lmb l55 32-pin rectangular leadless chip carrier 25 cy7c474C25jc j65 32-lead plastic leaded chip carrier commercial cy7c474C25pc p15 28-lead (600-mil) molded dip cy7c474C25ji j65 32-lead plastic leaded chip carrier industrial cy7c474C25dmb d43 28-lead (600-mil) sidebraze cerdip military cy7c474C25lmb l55 32-pin rectangular leadless chip carrier 40 cy7c474C40jc j65 32-lead plastic leaded chip carrier commercial cy7c474C40pc p15 28-lead (600-mil) molded dip cy7c474C40ji j65 32-lead plastic leaded chip carrier industrial cy7c474C40dmb d43 28-lead (600-mil) sidebraze cerdip military cy7c474C40lmb l55 32-pin rectangular leadless chip carrier dc characteristics parameter subgroups v oh 1, 2, 3 v ol 1, 2, 3 v ih 1, 2, 3 v il max. 1, 2, 3 i ix 1, 2, 3 i os 1, 2, 3 i cc 1, 2, 3 switching characteristics parameter subgroups t cy 9, 10, 11 t a 9, 10, 11 t rv 9, 10, 11 t pw 9, 10, 11 t lzr 9, 10, 11 t dvr 9, 10, 11 t hzr 9, 10, 11 t hwz 9, 10, 11 t sd 9, 10, 11 t hd 9, 10, 11 t efd 9, 10, 11 t hfd 9, 10, 11 t afed 9, 10, 11 t rae 9, 10, 11 t waf 9, 10, 11
CY7C470 cy7c472 cy7c474 14 package diagrams 28-lead (600-mil) sidebraze dip d43 32-pin rectangular leadless chip carrier l55 mil-std-1835 c-12 32-lead plastic leaded chip carrier
CY7C470 cy7c472 cy7c474 ? cypress s emiconduc tor corporation, 1995. the information contained herein is subject to change without noti ce. cypress semiconductor corporation assumes no re sponsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it c onvey or imply any license under patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress semiconduc tor products in life-support sy stems application implies that the manufacturer assumes all risk of such use and in doing so indemni fies cypress semiconductor against all charges. package diagrams 28-lead (600-mil) molded dip p15

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